1. Field of the Invention
The embodiments of the invention relate to integrated circuit fabrication and, in particular, to reducing plasma process induced damage to the gate dielectric.
2. Description of the Background
In the fabrication of integrated circuit devices, the gate dielectric can be damaged by exposure to a plasma used in processing steps that are performed on the device after the gate dielectric layer is formed. This plasma process induced damage, also known as plasma-charging damage, to the gate dielectric can degrade device performance and reduce yields. Processes that may cause damage to the gate dielectric include plasma etching of the polysilicon gate material to complete the transistors and plasma deposition and etching of metal and insulator layers used to form electrical connections between the transistors.
The exact mechanisms of plasma-induced damage are not completely understood, but it is known that the plasma can create an electrical potential across the gate dielectric that causes electrical current to flow through the gate. The current can damage or even destroy the gate dielectric. The degree of damage depends, in part, on the design of the device. It is believed that in many cases the electrical potential across the gate dielectric is created by the accumulation of charges from the plasma on exposed areas of metal or conductive polysilicons, which act as antennas. A high antenna-to-gate dielectric ratio causes more current to flow through the gate dielectric, and hence results in more damage. Thus, larger areas of metals or conductive polysilicons can result in more gate dielectric damage. Thinner gate dielectric layers are also more susceptible to plasma-induced damage. Because gate dielectrics are increasingly being made thinner to accommodate shrinking integrated circuit geometries, plasma-induced damage to the gate dielectric is becoming an increasingly significant problem.
Plasma-induced damage of the gate dielectric can be avoided or reduced by keeping the semiconductor wafer and gate dielectric cool during plasma processing. The amount of current that flows through the gate dielectric during plasma processing, and hence the potential for damaging the gate dielectric can increase exponentially with temperature. Cooling the gate dielectric makes the gate dielectric more resistive to current flow. In addition, for a given current flow, the probability of creating damage in the dielectric decreases as temperature is reduced. Thus, using low process temperatures can reduce the amount of damage that occurs to the gate dielectric.
However, high process temperatures may be necessary to obtain the desired results for the particular plasma process being performed on the wafer. For example, in the deposition of silicon dioxide films, which are used as insulators in integrated circuit devices, film characteristics are improved by the use of high temperatures. These film characteristics include film composition, propensity for moisture absorption, film shrinkage upon thermal cycling, wet etch rate, and gap fill capability. Deterioration of these film characteristics can cause production problems and compromise the stability of the device. Thus, any improvements in device performance or yields that would be gained by using low process temperature to reduce plasma-induced damage to the gate dielectric could be lost by damage done to other parts of the device by not using high process temperatures.
Plasma-induced damage to the gate dielectric may also be reduced by limiting the exposure of the integrated circuit device to plasma during fabrication. Thus, exposing the integrated circuit device to plasma only during the plasma process, and not while transferring the semiconductor wafer into and out of the reaction chamber, can reduce damage to the gate dielectric.
There are, however, advantages to continuously maintaining a plasma condition in the reaction chamber, resulting in the semiconductor wafer being exposed to plasma during transfer. These advantages include maintaining uniform conditions in the chamber, which helps to prevent films deposited on the interior surfaces from flaking, and, hence, reduces the number of particulates that fall onto the semiconductor wafer and damage the device. Continuously maintaining a plasma condition within the chamber also increases throughput, as no time is required to stop and start plasma and bring the reaction chamber to the appropriate operating conditions. Thus, improvements in device performance and yield that could be obtained by not exposing the semiconductor wafer to plasma during device transfer are offset by the benefits of continuously maintaining a plasma condition.